A circuit configured in one integrated circuit may execute processing of a plurality of steps. Sometimes, a step is required for a quick speed processing performance and a step is required for a low speed processing performance. In such a case, the operation speed of the integrated circuit follows the step of quick speed processing performance. Accordingly, in the integrated circuit, processing performance is left over while power consumption becomes large.
In order to reduce power consumption of the integrated circuit, a method for lowering a frequency of clock signal (clock frequency) is known as an effective method. Normally, an operable voltage is approximated as a primary function of operation frequency, and power consumption is proportion to a product of a square of a voltage and a frequency. Accordingly, by controlling the frequency and the voltage, the power consumption can be lowered. On the other hand, lowering the clock signal frequency means lowering the processing performance of the integrated circuit.
Recently, a programmable logic function changeable during operation of a function to be realized is proposed. The programmable logic function can change all or a part of logic configuration of a circuit during operation of the circuit. For example, a field programmable gate array (FPGA) has a logic configuration that is quickly changeable. Hereinafter, such circuits are called “a programmable logic circuit”.
In a method for operating the programmable logic circuit in time sharing, a unit circuit as a step required for a quick processing performance is operated for a long time while a unit circuit as a step sufficient for a slow processing performance is operated for a short time. In this case, a surplus of processing performance can be reduced.
In case of a logic circuit apparatus including a plurality of programmable logic circuits, a unit circuit (a processing) is assigned to each programmable logic circuit so that a total processing time of each programmable logic circuit is averaged. In addition to this, by changing a clock frequency and a supply voltage, the power consumption can be reduced. However, if each programmable logic circuit has a different operation feature (voltage and frequency), the operation feature of the circuit having the poorest feature controls. Accordingly, a programmable logic circuit of better power efficiency can not be effectively utilized.
On the other hand, a programmable information system having a self-repairing function is proposed in Japanese Patent Disclosure (Kokai) PH08-44581. In this system, components are automatically reconstituted against a fault so that normal functions can be reproduced. However, if a fault occurs in an arbitrary programmable logic circuit of the system, the system cannot cope with the fault.